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Philips Semiconductors
Product specification
N-channel enhancement mode TrenchMOS transistor array
FEATURES
* 30 m isolation transistor * 80 m spindle transistors * TrenchMOS technology * Logic level compatible * Surface mount package
D4
PHN70308
SYMBOL
isolation FET S4 G4
QUICK REFERENCE DATA VDS = 25 V ID = 5 A RDS(ON) 30 m
G6 G5 S6 D2 S5 D3
G7 S7 D1
(VGS = 10 V; isolation FET) RDS(ON) 80 m (VGS = 10 V; spindle FETs)
G1 S1
G2 S2
G3 S3
GENERAL DESCRIPTION
This product is used to drive high performance, three phase brushless d.c. motors in computer disk drives. The PHN70308 contains seven, n-channel enhancement mode trenchMOS transistors in a surface mounting plastic package. Six of the transistors can be configured as a three phase bridge to drive the spindle of a disk drive motor. The remaining transistor delivers power to the three phase bridge during normal operation. In the event of a power failure occurring whilst the motor is still spinning, this transistor isolates the computer power supply from the back emf generated by the motor. The PHN70308 is supplied in the surface mounting SOT341-1 (SSOP28) package.
PINNING
PIN 1,3 2 4 5,7 6 8 9,11 10 12 DESCRIPTION PIN drain 1 source 1 gate 1 drain 2 source 2 gate 2 drain 3 source 3 gate 3 16,17 18 20 21 23 24 26 27 13-15,19,22,25,28 DESCRIPTION source 4 gate 4 gate 5 source 5 gate 6 source 6 gate 7 source 7 drain 4
SOT341-1 (SSOP28)
28 Top view 15
1
14
May 1999
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode TrenchMOS transistor array
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS ID IDM Ptot Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Peak drain current per device (continuous operation) Peak current per device (pulse peak value) Power dissipation per device2 Total power dissipation in normal operation2 Storage & operating temperature CONDITIONS Tj = 25 C to 150C RGS = 20 k Tsp = 50 C1 spindle FETs; = 33.3% Isolation FET (dc) spindle FETs isolation FET Tsp = 50 C spindle FETs; = 33.3% isolation FET (dc) Tsp = 50 C spindle FETs; = 33.3% isolation FET (dc) MIN. - 55
PHN70308
MAX. 25 25 20 5 5 20 20 1.13 1.275 8 150
UNIT V V V A A A A W W W C
THERMAL RESISTANCES
SYMBOL Rth j-sp Rth j-a PARAMETER Thermal resistance junction to solder point Thermal resistance junction to ambient CONDITIONS isolation FET spindle FET device soldered to FR4 board, minimum footprint. isolation FET spindle FET TYP. 20 43 85 100 MAX. UNIT K/W K/W K/W K/W
1 Tsp is the temperature at the soldering point of the drain leads. 2 In normal operation, the isolation FET conducts continuously whilst each of the spindle FETs conducts for 33.3% of the time. The dissipation in the isolation transistor is given by:Pisolation = I 2xRDS(ON) (isolationFET) The dissipation in each of the spindle transistors is given by:Pspindle = 0.333xI 2xRDS(ON) (spindleFET) The total dissipation under these conditions is given by:Ptot = Pisolation + 6xPspindle With the motor being driven at 5 A and assuming Tj = 150C, the total dissipation is:Ptot = 25x0.03x1.7 + 0.333x25x0.08x1.7x6 = 8W Switching losses are assumed to be negligible. May 1999 2 Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode TrenchMOS transistor array
ELECTRICAL CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) RDS(ON) RDS(ON) IGSS IDSS Qg(tot) Qgs Qgd t on Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 10 A VDS = VGS; ID = 1 mA VGS = 10 V; ID = 4 A spindle FET isolation FET VGS = 4.5 V; ID = 2 A 95 38 102 46 10 10 0.1 5.4 17.6 0.4 1.4 1.6 5.7 MIN. 25 1.0 -
PHN70308
TYP. MAX. UNIT 1.5 60 27 80 30 150 60 136 51 100 100 0.5 V V m m m m m m nA nA mA nC nC nC nC nC nC
spindle FET isolation FET Drain-source on-state VGS = 10 V; ID = 4 A; Tj = 150C resistance spindle FET isolation FET Gate source leakage current VGS = 20 V; VDS = 0 V Zero gate voltage drain VDS = 20 V; VGS = 0 V; current Tj = 150C Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on time ID = 1 A; VDD = 20 V; VGS = 10 V spindle FET isolation FET spindle FET isolation FET spindle FET isolation FET VDD = 20 V; ID = 1 A; VGS = 10 V; RG = 6 ; resistive load spindle FET isolation FET spindle FET isolation FET VGS = 0 V; VDS = 20 V; f = 1 MHz spindle FET isolation FET spindle FET isolation FET spindle FET isolation FET
t off Ciss Coss Crss
Turn-off time Input capacitance Output capacitance Feedback capacitance
-
5.5 11 16 45 180 546 70 311 36 133
10 20 25 60 -
ns ns ns ns pF pF pF pF pF pF
May 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode TrenchMOS transistor array
SOURCE-DRAIN DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL IF IFRM VF trr PARAMETER Continuous forward diode current Repetitive peak forward diode current Diode forward voltage Reverse recovery time CONDITIONS spindle FET; = 33.3% isolation FET spindle FET isolation FET IF = 1.25 A; VGS = 0 V spindle FET isolation FET IF = 1.25 A; -dIF/dt = 100 A/s; VDS = 25 V spindle FET isolation FET Tsp = 50 C MIN. TYP. 0.8 0.8 20 25
PHN70308
MAX. 5 5 20 20 1 1 -
UNIT A A A A V V ns ns
Normalised Power Derating, Ptot (%)
100 90 80 70 60 50 40 30 20 10 0 0 20 40 60 80 100 120 140 160
Solder Point temperature, Tsp (C)
2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
Normalised On-state Resistance
-60
-40
-20
0
20 40 60 80 100 Junction temperature, Tj (C)
120
140
160
180
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tsp)
Fig.3. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 C = f(Tj)
Threshold Voltage, VGS(TO) (V) 3 2.75 2.5 2.25
Normalised Current Derating, ID (%)
120 100 80 60 40 20 0 0 20 40 60 80 100 120 140 160
Solder Point temperature, Tsp (C)
2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) minimum typical
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tsp); conditions: VGS 10 V
Fig.4. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
May 1999
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode TrenchMOS transistor array
PHN70308
1.0E-01
Drain current, ID (A) VDS = 5 V
100
Transient thermal impedance, Zth j-a (K/W)
D = 0.5 1.0E-02 minimum 1.0E-03 1 typical 1.0E-04 0.1 1.0E-05 T 1.0E-06 0 0.5 1 1.5 2 Gate-source voltage, VGS (V) 2.5 3 0.01 1E-06 single pulse P D tp D = tp/T 0.02 10 0.2 0.1 0.05
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
Pulse width, tp (s)
Fig.5. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C
Peak Pulsed Drain Current, IDM (A)
Fig.8. Transient thermal impedance (spindle FET). Zth j-sp = f(t); parameter D = tp/T
Transient thermal impedance, Zth j-a (K/W)
100
100
RDS(on) = VDS/ ID 10
tp = 10 us
10
D = 0.5 0.2
100 us 1 1 ms 1 10 ms D.C. 100 ms 0.1 0.1 1 10 Drain-Source Voltage, VDS (V) 100 0.1
0.1 0.05 0.02 single pulse
P D
tp
D = tp/T
T 0.01 1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
Pulse width, tp (s)
Fig.6. Safe operating area (spindle FET) Tsp = 25C ID & IDM = f(VDS); IDM single pulse; parameter tp
Peak Pulsed Drain Current, IDM (A)
Fig.9. Transient thermal impedance (isolation FET). Zth j-sp = f(t); parameter D = tp/T
Drain Current, ID (A) VGS = 10 V 4.5 V Tj = 25 C
100
8 7
RDS(on) = VDS/ ID tp = 100 us 10 1 ms
6 5 3.6 V 4
10 ms D.C. 1 100 ms
2 3
3.4 V 3.2 V 3V 1 2.8 V 2.6 V 0
0.1 0.1 1 10 Drain-Source Voltage, VDS (V) 100
0
0.2
0.4
0.6
0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V)
1.6
1.8
2
Fig.7. Safe operating area (isolation FET) Tsp = 25C ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.10. Typical output characteristics (spindle FET) Tj = 25 C; ID = f(VDS); parameter VGS
May 1999
5
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode TrenchMOS transistor array
PHN70308
Drain Current, ID (A) 10 10 V 9 8 7 6 5 4 3 2 1 2.6 V 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Drain-Source Voltage, VDS (V) 3.2 V 3V 2.8 V 3.4 V 3.6 V VGS = 4.5 V Tj = 25 C 5
Drain current, ID (A) VDS > ID X RDS(ON) 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Gate-source voltage, VGS (V) Tj = 25 C 150 C
Fig.11. Typical output characteristics (isolation FET) Tj = 25 C; ID = f(VDS); parameter VGS
Fig.14. Typical transfer characteristics (spindle FET) ID = f(VGS)
Drain-Source On Resistance, RDS(on) (Ohms) 0.5 2.8 V 3V 0.4 4 3.5 0.3 3 2.5 0.2 VGS =4.5 V 0.1 10V 2 1.5 1 0.5 0 0 0 1 2 3 4 Drain Current, ID (A) 5 6 7 8 3.2 V 3.4V 3.6 V Tj = 25 C 4.5 5
Drain current, ID (A) VDS > ID X RDS(ON)
150 C
Tj = 25 C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Gate-source voltage, VGS (V)
Fig.12. Typical on-state resistance (spindle FET) Tj = 25 C; RDS(ON) = f(ID); parameter VGS
Fig.15. Typical transfer characteristics (isolation FET); ID = f(VGS)
Transconductance, gfs (S) VDS > ID X RDS(ON) 5 Tj = 25 C 4 150 C
Drain-Source On Resistance, RDS(on) (Ohms) 0.2 3V 0.18 0.16 0.14 0.12 0.1 0.08 3.2 V 3.4V 3.6 V Tj = 25 C
6
3
2 0.06 0.04 0.02 0 0 1 2 3 4 5 Drain Current, ID (A) 6 7 8 9 10 0 0 0.5 1 1.5 2 2.5 3 Drain current, ID (A) 3.5 4 4.5 5 VGS =4.5 V 10V 1
Fig.13. Typical on-state resistance (isolation FET) Tj = 25 C; RDS(ON) = f(ID); parameter VGS
Fig.16. Typical transconductance (spindle FET) Tj = 25 C; gfs = f(ID)
May 1999
6
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode TrenchMOS transistor array
PHN70308
10 9 8 7 6 5 4 3 2 1 0
Transconductance, gfs (S) VDS > ID X RDS(ON) Tj = 25 C Gate-source voltage, VGS (V) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 2 3 4 5 6 Drain current, ID (A) 7 8 9 10 ID = 1A Tj = 25 C VDD = 20 V
150 C
1
2
3 4 5 Gate charge, QG (nC)
6
7
8
Fig.17. Typical transconductance (isolation FET) Tj = 25 C; gfs = f(ID)
Fig.20. Typical turn-on gate-charge characteristics (spindle FET); VGS = f(QG)
Gate-source voltage, VGS (V)
15 Capacitances, Ciss, Coss, Crss (pF) 1000 14 13 12 11 10 Ciss 9 8 7 100 Coss Crss 6 5 4 3 2 1 0 10 0.1 1 10 Drain-Source Voltage, VDS (V) 100
ID = 1A Tj = 25 C VDD = 20 V
0
2
4
6
8
10 12 14 16 Gate charge, QG (nC)
18
20
22
24
26
Fig.18. Typical capacitances (spindle FET) C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.21. Typical turn-on gate-charge characteristics (isolation FET); VGS = f(QG)
Source-Drain Diode Current, IF (A) Capacitances, Ciss, Coss, Crss (pF) 10000 5 VGS = 0 V 4.5 4 3.5 3 2.5 1000 2 Ciss 1.5 1 Coss Crss 100 0.1 1 10 Drain-Source Voltage, VDS (V) 100 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Source-Drain Voltage, VSDS (V) 150 C Tj = 25 C
Fig.19. Typical capacitances (isolation FET) C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.22. Typical reverse diode current (spindle FET) IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
May 1999
7
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode TrenchMOS transistor array
PHN70308
Source-Drain Diode Current, IF (A) 10 VGS = 0 V 9 8 7 6 5 4 3 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Source-Drain Voltage, VSDS (V) 150 C Tj = 25 C
Fig.23. Typical reverse diode current (isolation FET) IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
May 1999
8
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode TrenchMOS transistor array
MECHANICAL DATA
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1
PHN70308
D
E
A X
c y HE vMA
Z 28 15
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 14 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 8 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150AH EIAJ EUROPEAN PROJECTION
ISSUE DATE 93-09-08 95-02-04
Fig.24. SOT341-1 (SSOP28) surface mounting package.
Notes 1. This product is supplied in anti-static packaging. The leads must be protected against static discharge during transport or handling. 2. Refer to Integrated Circuit Packages, Data Handbook IC26. 3. Epoxy meets UL94 V0 at 1/8".
May 1999
9
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode TrenchMOS transistor array
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
PHN70308
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
May 1999
10
Rev 1.000

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